Digital encoding and decoding of high-definition video signals provides higher image resolution and more effective control of the storage, manipulation and display of the video signal over existing analog NTSC and
video systems. In an HDTV broadcast environment, for example, digital video data is encoded at a transmission end in accordance with a specified compressed bitstream syntax, such as the MPEG-2 standard, and decoded at a receiving end in accordance with a specified decoding process. The decoded video signal is reconstructed at the receiving end into picture frames that may be presented for display in a sequence with an HDTV resolution of 1920.times.1080 for example, or down-converted to a standard NTSC resolution of 720.times.480.
Decoding of compressed video signals is a memory-intensive process, especially for compressed high-definition video signals. Receivers adapted to decode compressed high-definition video signals generally require a significant amount of memory to store reference frame data and additional side information required in the decoding process. In the past, for example, a typical HDTV receiver for decoding a high-definition MPEG-2 video bitstream has required 12 MB or more of random-access-memory (RAM) to provide adequate memory storage of control information and reference frame video data in the receiver for reconstructing the transmitted picture frames.
Due to the relatively high cost of high speed memory, developers of HDTV receivers have sought to reduce the amount of memory required in the receiver for the decoding process. In the past, one approach has been to exploit only a portion of the compressed data in the transmitted HDTV signal to produce a decoded video signal representing an image of lesser resolution. For example, HDTV receivers have been designed in the past that decimate the decoded video data in accordance with a predetermined decimation scheme either before or after the inverse discrete transform function of the decoder to reduce the amount of video data that is stored in memory for reconstruction of the picture frames.
Decoded DCT coefficients may be decimated by masking a block of DCT coefficients of an 8.times.8 DCT coefficient array before the remaining coefficients are applied to the IDCT circuit of the decoder. Alternatively, particular rows and columns of pixel data generated by the IDCT circuit in an 8.times.8 pixel data array may be eliminated to reduce the amount of video data that must be stored. The reconstructed picture frames are then displayed at a lower NTSC resolution.
While this approach requires less memory in the decoder for reconstructing picture frames, the decimation scheme performed by the decoder may result in reduced picture quality as a portion of the decoded video data is eliminated during the decoding process. Furthermore, since only a limited portion of the decoded video data can be eliminated without completely sacrificing picture quality, the decimation scheme achieves only a modest amount of compression and is not readily adaptable for memory-scalable applications where the amount of decoder memory may vary among different decoding applications.
Thus, there is a need for a video decoder and method for decoding compressed high-definition video data that provides high quality reconstructed picture frames with an improved compression ratio. There is also a need for a video decoder and method for decoding compressed high-definition video data that reduces the amount of memory required in the decoder for reconstructing high quality picture frames. There is yet also a need for a video decoder and method for decoding compressed high-definition video data that provides memory-scalability for different decoding applications.